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NTE937M
Integrated Circuit JFET Input Operational Amplifier
Description: The NTE937M is a monolithic JFET input operational amplifier in an 8-Lead DIP type package incorporating well-matched, high voltage JFET's on the same chip with standard bi-polar transistors. This amplifier features low input bias and offset currents, low offset voltage and offset voltage drift, coupled with offset adjust which does not degrade drift or common-mode rejection. It is also designed for high slew rate, wide bandwidth, extremely fast settling time, low voltage and current noise and a low 1/f noise corner. Advantages: D Replaces Expensive Hybrid and Module FET OP Amps D Rugged JFET's Allow Blow-Out Free Handling Compared with MOSFET Input Device D Excellent for Low Noise Applications using either High or Low Source Impedance - Very Low 1/f Corner D Offset Adjust does not Degrade Drift or Common-Mode Rejection as in Most Monolithic Amplifiers D New Output Stage Allows use of Large Capacitive Loads (10,000pF) without Stability Problems D Internal Compensation and Large Differential Input Voltage Capability Applications: D Precision High Speed Integrators D Fast D/A and A/D Converters D High Impedance Buffers D Wideband, Low Noise, Low Drift Amplifiers D Logarithmic Amplifiers D Photocell Amplifiers D Sample and Hold Circuits Absolute Maximum Ratings: Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V Maximum Power Dissipation (at +25C, Note 1), Pd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V Input Voltage Range (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16V Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Maximum Operating Junction Temperature (Note 1), TJmax . . . . . . . . . . . . . . . . . . . . . . . . . . +100C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +150C Lead Temperature (During Soldering, 10sec), TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300C Thermal Resistance, Junction-to-Ambient (Note 1), RthJC . . . . . . . . . . . . . . . . . . . . . . . . . +155C/W Note 1. The maximum power dissipation for this device must be derated at elevated temperatures and is dictated by TJmax, RthJC, and the ambient temperature, TA. The maximum available power dissipation at any temperature is Pd = (TJmax - TA)/RthJC or the +25C Pdmax, whichever is less. Note 2. Unless otherwise specified, the absolute maximum negative input voltage is equal to the negative power supply voltage.
DC Electrical Characteristics: (TA = +25C, VS = 15V unless otherwise specified)
Parameter Supply Current Symbol ICC Test Conditions Min - Typ 5 Max 10 Unit mA
DC Electrical Characteristics: (VS = 15V, 0 TA +70C, THIGH = +70C unles otherwise specified)
Parameter Input Offset Voltage Average TC of Input Offset Voltage Change in Average TC with VOS Adjust Input Offset Current Input Bias Current Input Resistance Large Signal Voltage Gain Symbol VOS VOS/T Test Conditions RS = 50, TA = +25C Over Temperature RS = 50 TC/VOS RS = 50, Note 3 IOS IB RIN AVOL TJ = +25C, Note 4 TJ THIGH TJ = +25C, Note 4 TJ THIGH TJ = +25C TA = +25C, VO = 10V, RL = 2k Over Temperature Output Voltage Swing Input Common-Mode Voltage Range Common-Mode Rejection Ratio Supply Voltage Rejection Ratio VO VCM CMRR PSRR Note 5 RL = 10k RL = 2k Min - - - - - - - - - 25 15 12 10 10 - - Typ 3 - 5 0.5 3 - 30 - 1012 200 - 13 12 +15.1 -12 80 80 Max 10 13 - - 50 2 200 8 - - - - - - 100 100 Unit mV mV V/C V/C pA nA pA nA V/mV V/mV V V V dB dB
Note 3. The temperature coeficient of the adjust input offset voltage changes only a small amount (0.5V/C typically) for each mV of adjustment from its original unadjusted value. Common- mode rejection and open loop voltage gain are also unaffected by offset adjustment. Note 4. The input bias currents are junction leakage currents which approximately double for every 10C increase in the junction temperature, TJ. Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, Pd. TJ = TA + RthJC Pd where RthJC is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. Note 5. Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common practice.
AC Electrical Characteristics: (TA = +25C, VS = 15V unless otherwise specified)
Parameter Slew Rate Gain Bandwidth Product Settling Time to 0.01% Equivalent Input Noise Voltage Equivalent Input Current Noise Input Capacitance Symbol SR GBW ts eN iN CIN Note 6 RS = 100 f = 100Hz f = 1000Hz f = 100Hz f = 1000Hz Test Conditions AV = 5 Min 30 - - - - - - - Typ 50 20 1.5 15 12 0.01 0.01 3 Max - - - - - - - - Unit V/s MHz s nV/Hz nV/Hz pA/Hz pA/Hz pF
Note 6. AV = -5, the feedback resistor from output to input is 2k and the output step is 10V.
Pin Connection Diagram
Offset Null 1 Inverting Input 2 Non-Inverting Input 3 VEE 4
8
N.C.
7 VCC 6 5 Output Offset Null
8
5
.260 (6.6)
1
4
.390 (9.9) Max .155 (3.93)
.300 (7.62)
.100 (2.54) .300 (7.62)
.145 (3.68)

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